PLDgroundA new home for
programmable
logic.
PLDground is a modern workbench in the making. Write CUPL, inspect your device pins, and exercise your PLD design in one connected workspace.
Explore what’s comingPlanned for the web. Desktop for Windows, macOS, and Linux.
Name AddressDecoder;Device g16v8; PIN 2 = A0;PIN 3 = A1;PIN 4 = EN;PIN 19 = Y1; Y1 = EN & !A1 & A0;One connected workbench
From a logic equation
to a design you understand.
PLDground is being built for people working with programmable logic devices. It brings CUPL source, compilation, pin assignments, and functional simulation together, with a familiar IDE workflow and a clearer view of the design.
Write with focus.
A dedicated CUPL editor, project files, and build diagnostics—planned to keep the logic and the compiler’s feedback close together.
Follow every signal.
A device inspector that connects numbered package pins with full signal names, including the details that get crowded on denser packages.
Exercise your design.
Functional waveforms, test vectors, and expected outputs—planned to help you follow what your PLD does, one input change at a time.
A workbench taking shape
Good things take
a little groundwork.
PLDground is in development. We’ll update this page as the first release gets closer. A launch date has not been announced.
Building the first releaseWhat will PLDground do?
It is planned as a workbench for writing CUPL source, compiling PLD projects, inspecting device pins, and testing logic with a functional simulator.
Will it run in my browser?
A web application is planned, alongside desktop applications for Windows, macOS, and Linux. Access details will be published with the release.
Can I use it yet?
Public access is not available yet. This page introduces what we’re building; the workbench shown above is an illustrative preview.